In modern computers, clock signal timing for system memory is critical to assure robust operation of the memory channel. Many memory subsystems are designed in a daisy chain configuration. In a daisy chain configuration memory subsystem, a source synchronous operation originating from the memory controller hub (MCH) will send command, address, and control information with a memory channel clock to the dynamic random access memory (DRAM) devices, which are connected in series. In this scenario the first DRAM device in the chain receives the command/address/control information before the other DRAM devices, the second DRAM device receives the command/address/control information after first DRAM device but before the other DRAM devices, and so on until the last DRAM device receives the command/address/control information after all other DRAM devices.
Thus, each DRAM device is activated at a unique time based on the transit time needed for the command/address/control information to travel from the Memory Controller Hub (MCH) to each respective DRAM device. These unique activation times for each DRAM device means that each DRAM device sends data back to the MCH at a different and unique time, thus creating unequal latencies for all the devices. In today's computer systems, in order to protect from memory channel data corruption involving unequal DRAM latencies, the MCH must normalize the DRAM latencies. To accomplish DRAM latency normalization the MCH can incorporate additional circuitry to buffer the incoming data. Though, this method is not desirable because of the extra circuitry added within the MCH. The MCH can also accomplish this by adding extra timing delays to its memory channel to eliminate the possibility of memory corruption because of the discrepancy in DRAM latencies. This solution is also not desirable because of added delays in MCH timing lowers system performance.